The present invention relates to a method and to a bus interface employing a memory in an integrated circuit which is used to link a bus with an application device to be controlled by the bus.
The IEEE1394 bus is a low cost, high performance serial bus. It has a read/write memory architecture and a highly sophisticated communication protocol. Data rates of 100, 200 or 400 Mbit/s can be transmitted in nearly real time. Simultaneously, data can be transmitted bi-directionally. The first ten bits of transmitted address values refer to one of up to 1023 possible IEEE1394 bus clusters. The following six bits of the transmitted address values refer within a specific cluster to one of up to 63 nodes to which an application or device is assigned. Data between nodes can be exchanged without interaction of a host controller. Devices can be connected to or disrupted from the network at any time, allowing a plug and play behaviour.
The standardised cable connection for the nodes has a length of 4.5 m and contains three twisted cable pairs of which two pairs serve for data and control information transmission and the further pair carries supply voltages of 8V to 40V. Three level coding is used: HIGH (H), LOW (L), and HIGH IMPEDANCE (Z). H overrides L, L overrides Z. The characteristic impedance is 110 xcexa9. There is also a version IEEE1394-1995 of the bus specification including only two twisted pairs of cables on which no power supply voltage is present. The communication protocol has three layers: physical layer, link layer, and transaction layer. Typically, the transaction layer is realised by firmware whereas the other layers are implemented using chip sets.
The physical layer contains analog transceivers and a digital state machine. It handles bus auto-configuration and hot plug. It reclocks, regenerates and repeats all packets and forwards all packets to the local link layer. It carries out-packet framing, for example speed code, prefix, and packet end assembling. It arbitrates and transmits packets from the local link layer. Available IC types are e.g. TSB11C01, TSB11LV01, TSB21LV03, and TSB41LV03 of Texas Instruments, MB86611 of Fujitsu, and 21S750 of IBM.
The link layer performs all digital logic. It recognises packets addressed to the node by address recognition and decodes the packet headers. It delivers packets to higher layers and generates packets from higher layers. It works either isochronous for AV data use or asynchronous for control data use.
In the isochronous mode a channel having a guaranteed bandwidth is established. There is a defined latency. The transmission is performed in 125 xcexcs time slots or cycles. Headers and data blocks of a packet have separate CRCs (cyclic redundancy check). This mode has a higher priority than the asynchronous data transfer mode.
The asynchronous mode is not time critical, but safe. It operates as an acknowledged service with a busy and retry protocol. Fixed addresses are used. Transmission takes place when the bus is idle. The asynchronous mode handles read request/response, write request/response, and lock request/response. It performs cycle control, CRC generation and validation. Available link layer IC types are e.g. TSB12C01A, TSB12LV21, TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 of Philips.
The transaction layer implements asynchronous bus transactions:
Read request/read response
Write request/write response
Lock request/lock response.
As mentioned above it can be implemented by software running on a microcontroller, such as e.g. the i960 of SparcLite. There may also be an AV (audio video) layer carrying out device control, connection management, timestamping, and packetising.
In IEEE1394 systems, the link layer acts as an interface between an external application and the IEEE1394 bus (through the physical layer).
The external application can be for example a consumer device, such as a set-top-box or a VCR or a DVD player, which delivers/receives latency critical isochronous data and non-latency critical asynchronous data.
The asynchronous data packets are used for the controlling operations or register read/write/lock operations. Isochronous data packets contain information items like video-/audio data.
For timing decoupling of IEEE1394 bus and application an on-chip memory is used. Because of strongly limited link layer IC on-chip memory capacity it is important to save space when processing with this memory. In case of an ASIC solution for the link layer IC a FIFO (first-in first-out memory) can be used to connect the IEEE1394 bus with the application device and to organise the handling of the asynchronous and isochronous data packets.
It is possible to separate the memory capacity into fixed areas for asynchronous and isochronous data. However, it is advantageous to split the memory capacity in a flexible way in order to be able to meet the requirements for any specific service. Then the memory capacity remaining for other services is to be managed efficiently in order to meet the speed and address requirements. One problem is the efficient management of latency critical isochronous data and non-latency critical asynchronous data within the on-chip memory.
According to the invention, the on-chip memory is prevented on the fly from storing packets containing transmission errors. This feature is true for all asynchronous data packets and in special cases also for isochronous data packets.
In particular, the FIFO memory of the link layer chip is separated into three areas: asynchronous reception area, asynchronous transmission area and isochronous data packet area.
In the asynchronous mode the reception and transmission of IEEE1394 bus data packets is performed in an independent way, whereas in the isochronous mode the reception and transmission of a data packet is carried out in a sequential way, thereby accessing the same memory area.
In receiving mode the data packets coming from the IEEE1394 bus are written word by word into the corresponding memory area. According to the IEEE1394 bus specification the first part of a data packet is defined as the packet-header which is followed by the packet (user) data in the second part.
There are two CRC checkwords (cyclic redundancy check) in an asynchronous IEEE1394 data packet. The first one is appended to the packet header and the second one is appended to the packet or payload data. Due to this specific location of the CRC checkwords within the received packet datastream it is not possible to process the CRC checkwords before writing a data packet into memory. There are at least three ways to process an asynchronous data packet:
a) write all data packet completely into the memory without CRC check. Upon reading the data packets from the memory, the application device will carry out the header CRC check and the packet data CRC check on all data packets and skip the erroneous data packets;
b) in each case, write a complete data packet into the memory thereby carrying out immediate CRC check on this data packet and mark it as xe2x80x98erroneousxe2x80x99 if true for the header CRC check and/or the packet data CRC check. Upon reading the data packets from the memory, the application device will check the marking of all data packets and skip the erroneous data packets;
c) in each case, carry out xe2x80x98on-the-flyxe2x80x99 a header CRC check or a header CRC check and a packet data CRC check on the incoming data packet using a dedicated CRC check unit and its register(s), and do not write the incoming data packet or its packet data into the memory if the header and/or the packet data is erroneous. Then, initialised by the first header data byte, overwrite the erroneous data packet or packet data, respectively, with the next incoming data packet or packet data.
Advantageously, alternative c) is performed because it saves as much memory space as possible.
Isochronous data packets have a similar structure. The packet header is followed by a header CRC checkword which itself is followed by a payload data field to which a data CRC checkword is attached. This payload field, or data field, contains at the beginning an information field denoted common isochronous packet (CIP) header, describing the structure of the following data. This item of information is not necessarily written into the memory.
Source data packets may contain data groups which have a pre-known fixed data length which does not match the data length of the IEEE1394 payload data field. E.g. MPEG transport packets do have a standardised length of 188 bytes which is different from the length of 104 bytes of the IEEE1394 payload data field. Therefore one MPEG transport packet can be transmitted partially within one, two, four or eight succeeding IEEE1394 payload data fields.
There are at least six ways to process an isochronous data packet:
d) in each case, if a data packet is recognised to be addressed to the application device, write it completely into the memory without header CRC check and data field CRC check. Upon reading the data packets from the memory, the application device will carry out both types of CRC checks on all data packets and skip the erroneous data packets;
e) in each case, write a complete data packet into the memory, carry out immediate header CRC check and/or data field CRC check on this data packet and mark it as xe2x80x98erroneousxe2x80x99 if true for the header and/or the data field. Upon reading the data packets from the memory, the application device will check the markings of all data packets and skip the erroneous headers and/or data fields. In some cases it may be possible that one part of a data packet can be used although the other part is erroneous;
f) in each case, carry out xe2x80x98on-the-flyxe2x80x99 a header CRC check on the incoming data packet using a dedicated CRC check unit and its register(s). Do not write the incoming data packet into the memory if the header is erroneous. Other-wise, either evaluate the header directly and write the data field into the memory including the data field CRC, or write the header and the data field into the memory including the data field CRC. Data field CRC check is performed later;
g) in each case, carry out xe2x80x98on-the-flyxe2x80x99 a header CRC check on the incoming data packet using a dedicated CRC check unit and its register(s). Do not write the incoming data packet into the memory if the header is erroneous. Other-wise, either evaluate the header directly and write the data field into the memory including the data CRC thereby performing data field CRC check, or write the header and the data field into the memory thereby performing data field CRC check, and mark the data field as xe2x80x98erroneousxe2x80x99 if true. The marking can be stored in the memory together with the data field. Upon reading the payload data field, or the header and the payload data field, from the memory the application device will check the marking and skip the erroneous payload data fields or headers, respectively;
h) in each case, carry out xe2x80x98on-the-flyxe2x80x99 a header CRC check and a data field CRC check on the incoming data packet using a dedicated CRC check unit and its register(s). Do not write the incoming data packet into the memory if the header and/or the data field is erroneous;
i) in each case, carry out xe2x80x98on-the-flyxe2x80x99 a header CRC check on the incoming data packet using a dedicated CRC check unit and its register(s). Do not write the incoming data packet into the memory if the header is erroneous. Other-wise, either evaluate the header directly and write the source packet data from the data field into the memory thereby performing data field CRC check, or write the header and the data field into the memory thereby per-forming data field CRC check, and mark source packet data or the data field, respectively, as xe2x80x98erroneousxe2x80x99 if true. In addition, the above described data length is checked. In case the pre-known data length of a source packet is not achieved, this source packet can be marked as xe2x80x98erroneousxe2x80x99. That packet will be overwritten by the next packet. Upon reading the header and the payload data field from the memory the application device will check the marking and skip the erroneous payload data fields or headers, respectively.
Advantageously, alternative i) is performed because it saves as much memory space as possible and because it allows to not only detect transmission errors but also source packet generation errors.
It is one object of the invention to disclose a method for employing a memory in an integrated circuit which is used to link a bus with an application device to be controlled by said bus, wherein the required memory capacity is minimised.
It is a further object of the invention to disclose an apparatus which utilises the inventive method.
In principle, the inventive method employs a memory in an integrated circuit which is used to link a bus with an application device to be controlled by said bus, wherein data packets are sent via said bus to said application device which include header data to which a first error protection code is assigned and payload data to which a second error protection code is assigned, and wherein said payload data are intended to be intermediately stored in said memory, and wherein for a received current data packet in each case said first error protection code is evaluated and if this evaluation indicates that the header data of the current data packet have been received erroneously, at least payload data of the current data packet are not written into said memory. In case header data of said current data packet have been written into said memory and the evaluation of said first error protection code or said second error protection code, respectively, indicates that the header data resp. payload data of the current data packet have been received erroneously, the header data of the next data packet to be received can overwrite the header data of the current data packet in said memory.
In principle the inventive bus interface is suited for linking a bus with an application device to be controlled by said bus, wherein data packets are sent via said bus to said application device which include header data to which a first error protection code is assigned and payload data to which a second error protection code is assigned, and includes:
a memory in an integrated circuit into which said payload data are intended to be intermediately stored;
evaluation means which in each case evaluate said first error protection code of a received current data packet, wherein, if the evaluation result indicates that the header data of the current data packet have been received erroneously, at least payload data of the current data packet are not written into said memory.
In case header data of said current data packet have been written into said memory and the result from said evaluation means concerning said first error protection code or said second error protection code, respectively, indicates that the header data resp. payload data of the current data packet have been received erroneously, memory address generation means can control said memory such that the header data of the next data packet to be received overwrite the header data of the current data packet.